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ACOPS Automatic CPU Overheating Prevention System (GigaByte) "A-COPS"

ACP Average CPU Power (CPU, TDP)

ALU Arithmetic and Logic Unit (CPU)

APU Accelerated Processing Unit (AMD, CPU, GPU)

ATC Address Translation Cache (CPU)

AVX Advanced Vector eXtensions (CPU, Intel)

BF Bus Fraction [pin] (Intel, Pentium, CPU)

BGA Ball Grid Array (IC, CPU)

BHT Branch History Table (CPU)

BLW Bus Locked Write (Intel, CPU)

BP Base Pointer [register] (CPU, Intel, Assembler)

BPU Branch Prediction Unit (CPU, MMX, Intel)

BPU Branch Processing Unit (CPU)

BRIL Bus Read Invalidate Line (Intel, CPU, BWIL)

BRL Bus Read Line (Intel, CPU, BWL)

BTB Branch Target Buffer (CPU)

BTLB Block Translation Look-aside Buffer (CPU)

BTS Branch Tree Store (Intel, CPU)

BWIL Bus Write Invalidate Line (Intel, CPU, BRIL)

BWL Bus Write Line (IIntel, CPU, BRL)

CBGA Ceramic Ball and Grid Array (IC, CPU)

CISC Complex Instruction Set Computer (CPU)

CLIW Configurable Long Instruction Word (IC, CPU)

COS Clip On Socket (CPU)

CPGA Ceramic Pin Grid Array (IC, CPU)

CPR CPU Parameter Recall (Asus), "C.P.R."

CPU Central Processing Unit

CPUID Central Processing Unit IDentifier (CPU)

CS Code Segment [register] (CPU, Intel, Assembler)

CSDC Code Segment Descriptor Cache [register] (CS, Intel, CPU)

CT Clackamas Technology (Intel, Pentium, CPU)

CWP Current Workspace Pointer (SPARC, CPU)

DCU Data Cache Unit (CPU, POWER)

DERAT Data cache Effective to Real Address Translation [table] (Power4, IBM, CPU, ERAT)

DI Destination Index [register] (CPU, Intel, Assembler)

DS Data Segment [register] (CPU, Intel, Assembler)

DSDC Data Segment Descriptor Cache [register] (DS, Intel, CPU)

DTLB Dual Translation Lookaside Buffer (CPU)

DTS Digital Thermal Sensor (Intel, IC, CPU)

DVID Dynamic - Voltage IDentification (Intel, CPU), "D-VID"

EA Effective Address (Power4, IBM, CPU)

EBGA Enhanced Ball Grid Array (BGA, CPU, IC)

ECC Error Correction Circuit (CPU, POWER)

EIEIO Enforce In-order Execution of Input/Output (PowerPC, I/O, CPU)

EIP Extended Instruction Pointer [register] (CPU, Intel, Assembler)

EPIC Explicit Parallelism Instruction Computing (Intel, CPU, VLIW)

ERAT Effective to Real Address Translation [table] (Power4, IBM, CPU, EA, RA)

ES Extra Segment [register] (CPU, Intel, Assembler)

ESDC Extra Segment Descriptor Cache [register] (ES, Intel, CPU)

EU Execution Unit (CPU)

EVP Enhanced Virus Protection (AMD, CPU)

FCPGA Flip Chip Pin Grid Array (IC, CPU), "FC-PGA"

FIFO First In First Out (CPU)

FLOPS FLoating-point Operations Per Second (CPU)

FPBGA Fine Pitch Ball Grid Array (IC, CPU)

FPU Floating Point Unit (CPU)

FRF Floatingpoint Register File (DEC, Alpha, CPU)

FXU FiXed point Unit (POWER, CPU)

GCT Group Completion Table (Power4, IBM, CPU)

GDTRC Global Descriptor Table Register Cache (GDT, Intel, CPU)

GFLOPS Giga FLoating-point Operations Per Second (CPU)

GIPS Giga Instructions Per Second (CPU)

GPR General Purpose Register (CPU)

HT Hyper-Threading (Intel, Pentium, SMT, CPU)

HTC Hardware Thermal Controller (AMD, IC, CPU)

ICU Instruction Cache Unit (CPU, POWER)

IDTRC Interrupt Descriptor Table Register Cache (IDT, CPU, Intel)

IERAT Instruction cache Effective to Real Address Translation [table] (Power4, IBM, CPU, ERAT)

IFAR Instruction Fetch Address Register (Power4, IBM, CPU)

IFP Instruction Fetch Pipeline (Motorola, CPU)

IHS Integrated Heat Spreader (CPU)

ILP Instruction Level Parallelism (CPU)

IOPLL IO Phase Lock Loop (IO, Intel, CPU)

IP Instruction Pointer [register] (CPU, Intel, Assembler)

IPI Inter-Processor Interrupt (CPU, SMP)

IRF Integer Register File (DEC, Alpha, CPU)

ISA Instruction Set Architecture (CPU)

ITLB Instruction Translation Look-aside Buffer (CPU)

IU Integer Unit (CPU)

JTB Jump Trace Buffer (CPU)

LBR Last Branch Recording (Intel, CPU, IC)

LDT Local Descriptor Table (CPU, Intel)

LDTR Load Descriptor Table Register (CPU, Intel, Assembler, IC)

LDTRC Local Descriptor Table Register Cache (LDT, Intel, CPU)

LER Last Exception Record (MSR, Intel, CPU)

LFB Linear Frame Buffer (CPU, VESA)

LIW Long Instruction Word (CPU)

LMQ Load Miss Queue (Power4, IBM, CPU)

LRQ Load Reorder Queue (Power4, IBM, CPU)

LSU Load/Store Unit (Power4, IBM, CPU)

LT Lagrande Technology (Intel, Pentium, CPU)

MCE Machine Check Exception (Intel, CPU)

MCM MultiChip Module (CPU)

MFLOPS Million FLoating-point Operations Per Second (CPU)

MIMD Multiple Instruction [stream], Multiple Data [stream] (CPU)

MIPS Million Instructions Per Second (CPU)

MIS Micro Instruction Sequencer (Intel, CPU)

MISD Multiple Instruction [stream], Single Data [stream] (CPU)

MMX MultiMedia eXtensions (Intel, CPU)

MOB Memory Ordering Buffer (Intel, CPU)

MTRR Memory Type Range Register (CPU, Pentium Pro, IC)

MVI Motion Video Instructions (DEC, CPU, Alpha)

NCL Null Convention Logic (CPU)

NEM No-Eviction Mode (Intel, HT, CPU)

NSP Native Signal Processing (Intel, CPU)

OBGA Organic Ball Grid Array (BGA, IC, CPU)

OEP Operand Execution Pipelines (Motorola, CPU)

OOO Out Of Order [execution] (Intel, Pentium, CPU)

OPS Operations Per Second (CPU)

P2CC2P PCI to CPU / CPU tp PCI [concurrency] (BIOS, PC, PCI, CPU), "P2C/C2P"

PAX Pixel Addressing eXtensions (Intel, RISC, CPU)

PCR Processor Configuration Register (Motorola, CPU)

PEBS Precise Event Based Sampling (Intel, CPU)

PGA Pin Grid Array (IC, CPU)

PISW Process Interrupt Status Word (CPU, Assembler)

PM Protected Mode (Intel, CPU)

POEP Primary Operand Execution Pipeline (Motorola, CPU), "pOEP"

PPGA Plastic Pin Grid Array (IC, CPU)

PQFP Plastic Quad Flat Package (CPU)

PRF Physical Ref file (CPU, Intel)

PSI Power Status Indicator (Intel, CPU)

PST P-State Transitions (CPU)

QC Quad Core (CPU)

RA Real Address (Power4, IBM, CPU)

RAT Register Allocation Table (Intel, CPU)

RIP Return Instruction Pointer (CPU, RAM)

RISC Reduced Instruction Set Code (CPU)

RPP Relative Processor Performance (CPU, Cray)

SCU System Control Unit (CPU, POWER)

SDQ Store Data Queue (Power4, IBM, CPU, SRQ)

SECC Single Edge Connector Case (CPU)

SFP Saved Frame Pointer (CPU, RAM)

SI Source Index [register] (CPU, Intel, Assembler)

SIMD Single Instruction [stream], Multiple Data [stream] (CPU)

SISD Single Instruction [stream], Single Data [stream] (CPU)

SLB Segment Lookaside Buffer (CPU, Power4, IBM)

SMM System Management Mode (CPU)

SMT Simultaneous MultiThreading (CPU)

SOEP Secondary Operand Execution Pipeline (Motorola, CPU), "sOEP"

SP Stack Pointer [register] (CPU, Intel, Assembler)

SQFP Shrink Quad Flat Package (CPU)

SRQ Store Reorder Queue (Power4, IBM, CPU)

SS Stack Segment [register] (CPU, Intel, Assembler)

SSDC Stack Segment Descriptor Cache [register] (SS, Intel, CPU)

TCP Tape Carrier Package (CPU)

TDP Thermal Design Power (CPU, ACP, SDP)

TEC Trace Execution Cache (Intel, Pentium, CPU)

TFLOPS Tera FLoating-point Operations Per Second (CPU)

TIM Thermal Interface Material (CPU)

TLB Translation Lookaside Buffer (CPU)

TLP Thread Level Parallelism (CPU)

TR Task Register (CPU, Intel, Assembler, IC)

TSSDC Task State Segment Descriptor Cache (CPU)

USWC Uncached Speculative Write Combining (CPU)

UTLB Unified Translation Look-aside Buffer (CPU)

VID Voltage IDentification (CPU)

VIF Virtual Interrupt Flag (Intel, CPU)

VIS Virtual Instruction Set (Sun, CPU)

VLIW Very Long Instruction Word (CPU, IC)

VMP Virtual MultiPorting (POWER, CPU)

VT Vanderpool Technology (Intel, Pentium, CPU)

WCB Write Combining Buffer (CPU)

ZE Zentraleinheit (CPU)

ZISC Zero Instruction Set Computer (CPU)


Es wurden insgesamt 164 Akronyme gefunden.

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